The invention relates to a low-distortion “degenerated bypass CMOS (complementary metal oxide semiconductor) transconductor” that is more linear than a basic CMOS inverter/transconductor or a conventional “degenerated” CMOS transconductor. The invention also relates to achieving improved resilience or “robustness” of the degenerated bypass CMOS transconductor with respect to process, supply voltage and temperature (PVT) variation, compared to the resilience of either a basic CMOS transconductor or a conventional degenerated CMOS transconductor with respect to PVT variation.
Transconductance is a property of certain electronic components. Conductance is the reciprocal of resistance. Transconductance is the ratio of the AC current variation at the output of a component to the AC voltage variation at its input. A “transconductor” (which may be represented by the symbol Gm or gm) can be considered to be a circuit or circuit element having transconductance and which converts an input voltage signal into a proportional current. Many electronic devices, such as BJTs (bipolar junction transistors), MOSFETs (metal oxide semiconductor field effect transistors), and vacuum tube triodes can be useful as transconductors when properly biased. The transconductor is a versatile building block used in many analog and mixed-signal circuit applications such as continuous-time filters, delta-sigma modulators, variable gain amplifiers or data converters, and a wide range of other circuits such as filters, amplifiers, and oscillators.
FIG. 1 A shows a conventional CMOS inverter 1l including a P-channel (PMOS) transistor MP1 and a N-channel (NMOS) transistor MN1 coupled between a supply voltage VDD and a physical ground conductor and having their gates connected to an input signal Vin and their drains connected to an output conductor 2 in which an output current io is generated.
The output current of transconductor 1 (also referred to as CMOS inverter 1) shown in FIG. 1A can be approximated for low frequencies by a Taylor series expansion as:
      i    o    ≈                    (                              g            mn                    +                      g            mp                          )            ⁢              V        in              +                  (                              g            mn            ′                    +                      g            mp            ′                          )            ⁢              V        in        2            ⁢              /            ⁢      2        +                  (                              g            mn            ″                    +                      g            mp            ″                          )            ⁢              V        in        3            ⁢              /            ⁢      6        +    …    ≈                    g        m            ⁢              V        in              +                  g        m        ′            ⁢              V        in        2            ⁢              /              +                  g        m        ″            ⁢              V        in        3            ⁢              /            ⁢      6        +    …  where (gmn, gmp, gm), (g′mn, g′mp, g′m), and (g″mn, g″mp, g″m) are the transconductance and its first and second derivatives of the NMOS, PMOS and CMOS devices, respectively, wherein the effects of voltage swing of the output current io in conductor 2 and its higher order derivative terms are neglected. Yin represents the small-signal gate-to-source voltage of the NMOS transistor MN1 when two interfering signals at frequencies f1 and f2 are present at the input of the transconductor. Due to non-linear distortion, new frequency components at frequencies 2f1-f2 and 2f2-f1 are created at the output in addition to the fundamental input frequencies f1 and f2. If a weak signal to be sensed is present at frequencies 2f1-f2 or 2f2-f1, it is corrupted by these distortion components. If a transconductor is linear, the distortion components are very small. The two graphs included in FIG. 1A to illustrate distortion effects due to the two interference frequencies f1 and f2. For a CMOS transconductor circuit to be resilient or “robust” with respect to interference signals, it should be as linear as possible.
The conventional CMOS inverter 1 of FIG. 1A has various advantages and limitations with respect to its use as a transconductor. CMOS inverter 1 is an efficient transconductor because the same bias current flows through both the NMOS and PMOS transistors, resulting in addition of their transconductances gmn and gmp. This leads to a higher gm/ID ratio or higher power efficiency, where gm is the transconductance and ID is the DC bias current through transistors MP1 and MN1. A purely differential circuit does not suffer from “even order distortion”, so it is desirable to reduce the “odd order distortion” coefficients more than the even order ones because a MOS transistor is approximately a square-law device having low odd order distortion. Furthermore, a CMOS transconductor provides cancellation of non-linear current components in its N-channel and P-channel transistors using a linearization technique known as “complementary derivative superposition”. The non-linear distortion properties of a CMOS transconductor may be demonstrated by the simulated output drain currents of the NMOS and PMOS transistors and their respective derivatives, as shown in the graphs of FIG. 1B.
In Equation 1, the second and third order distortion components are proportional to the first and second order derivatives gm′ and gm″ of the transconductance gm respectively. These derivatives are shown in graphs C and D of FIG. 1B. Note that there is cancellation of both first and second order derivatives of the transconductances of the NMOS transistor and also the PMOS transistor leading to lower magnitudes of the corresponding derivatives of the CMOS inverter/transconductor. This leads to cancellation of distortion.
In particular, FIG. 1B shows a bias point Vin≈0.55 volts as indicated by dotted lines in graph D (the relevant graphs are graphs C, D, and E) for a properly designed CMOS transeonductor, where the second order derivative gm″ is approximately zero for the N-channel transistor MN1 and the P-channel transistor MP1 in FIG. 1A. C-1, C-2 and C-3 are the first derivatives g′m, g′mn, and g′mp, of the CMOS, NMOS and PMOS devices with respect to input voltage Vin, respectively. The vertical axis dimension in graph C is milli-Siemens per Volt (mSIV2). Similarly, the vertical axis dimension in graph D is Siemens per Volt Square (S/V2). The vertical axis dimension in graph E isVIIP3, which is normally given in Volts but can also be expressed as dBs which is the same as 20×Log10(VIIP3 in Volts).
A MOS transistor is approximately a square-law device, especially when it is biased at the peak of its first order derivative g′m, shown in graph C of FIG. 1B. At this bias point, its second order derivative g′″m is zero. Unfortunately, at this bias point the first order derivatives g′m are at their maximum values. (The first order derivative g′m of the transeonductor is proportional to the second order distortion term g′mV2in/2 Similarly, the second order derivative g″m of the transeonductor is proportional to the third order distortion term g″mV3in/6.) A small mismatch between the two transistor's third order distortion terms can lead to a large variation PIIP3. (The term “IIP3” is the “third order input intercept point” or “third order intercept point”, which is the point at which the extrapolated output power in the third-order product and the fundamental tone intersect, assuming that the amplifier's distortion is predominantly third-order distortion. (In practice, when the input power levels are increased the higher order (5th, 7th, etc.) distortion terms start to dominate.) IIP3 is a very useful parameter to predict low-level intermodulation effects. Furthermore, the peak PIIP3 values shown in FIG. 1B are difficult to achieve for practical input voltage signal swings, as the input voltage does not stay at these peaks leading to lower worst case PIIP3 values. (The input voltage Vin sweeps across a range of values along the x-axes of FIG. 1B. Thus in practice the IIP3 peaks become less relevant.)
One application for a highly linear CMOS transconductor would be in a Software Defined Radio (SDR) system. SDR is a known technique that provides an economically viable solution to cope with the rapidly increasing number of wireless communication standards such as GSM, UMTS, LTE, etc. and the various associated frequency bands being allocated in various countries. Due to lack of linear and tunable RF filtering alternatives, a SDR receiver front end circuit must contend with strong interfering signals that can degrade its performance. To combine receiver operation in a broad band of frequencies with suitable impedance matching and low noise, receivers having noise cancellation have been used.
FIG. 2 shows a schematic diagram of a SDR receiver that utilizes frequency translated noise cancellation (FTNC). Since the main signal path can be very linear due to the use of a resistor and the distortion can be reduced by conventional noise/distortion cancellation techniques, the low noise transconductance amplifier (LNTA) in the auxiliary path becomes a “bottleneck” for out-of-band linearity of the SDR receiver, A LNTA is used in many recent CMOS receiver front end circuits. However, there is a substantial need for a technique to improve the linearity of the LNTA in a robust way that is insensitive to PVT variations.
A well-designed CMOS transconductor, while being quite linear due to use of non-linearity cancellation effects, could fail to meet certain very high linearity requirements. In many applications, a transconductor must meet guaranteed linearity specifications independently of process, component mismatch, and other variations. In the circuit of FIG. 3, a known linearization technique is used to achieve a better linearity specification than is achievable with a basic CMOS inverter/transconductor while nevertheless exploiting the above-mentioned non-linearity cancellation effect that is inherent in a CMOS inverter. The resulting “improved CMOS transconductor” is obtained using negative feedback, by using resistive degeneration as shown in FIG. 3.
In FIG. 3, a resistively degenerated N-channel transistor circuit 3 includes a N-channel MOS transistor MN1 and a degeneration resistor R coupled between the source of transistor MN1 and a fixed ground reference. An input voltage Vin is applied to the gate of transistor MN1 nd a drain current IDS flows through its drain and source and also through degeneration resistor R and provides a well-known resistive degeneration technique for improving linearity of CMOS transconductors.
Referring to FIG. 3, the gate of degenerated N-channel transistor MN1 is excited by two test tones of the input voltage Vin at closely spaced frequencies F1 and F2. The resulting second order distortion is shown in the graph of FIG. 3, and causes the drain current IDS, and hence the source voltage VS, to have second order distortion components at frequencies |F1-F2|, 2F1, and 2F2. The source voltage VS interacts with the gate voltage Vin through the second order distortion and causes the third order distortion components in the drain current IDS at frequencies 2F1-F2 and 2F2−F1. Essentially the same effect occurs in a degenerated PMOS transistor MP1 of a CMOS transconductor.
Due to the inherent square-law nature of a MOS transistor, the second order distortion component which dominates the non-linearity is converted to third order and other odd-order non-linearity components. This is particularly true in situations where the degeneration factor gmR is low. Negative feedback in these cases tries to suppress the total signal distortion, which is otherwise dominated by second-order distortion. The source voltage VS produced in response to IDS has second order distortion components at frequencies F2−F1, 2F1, 2F2 and F1+F2 as illustrated in FIG. 113. The square-law nature of MOSFETs MN1 mixes these second order VS tones on the source of transistor MN1 with Vin tones on the gate of transistor MN1, which also results in third order distortion components in the output current io at frequencies 2F1−F2 and 2F2−F1. (A MOSFET has square-law behavior, wherein the gate-source voltage is squared. For example, if “a” is the gate voltage and “b” is the source voltage, then (a−b)2=a2+b2−2ab. The term ab is a mixing term which multiplies a by b. A similar effect happens in the degenerated P-channel transistor MP1 of a degenerated CMOS transconductor, and when the two output currents are combined or added the degenerated CMOS transconductor/inverter can have higher third order distortion than a basic CMOS inverter under the same biasing conditions.
Especially for low loop gain in a degenerated CMOS transconductor, the square-law term of a MOSFET can be problematic because it indirectly generates third-order distortion and higher order non-linearity and that third-order distortion is dependent on PVT variations. Thus, if source degeneration resistors are added to a basic CMOS inverter/transconductor, the quadratic drain currents IDS cause the source voltages VS to contain quadratic terms, and the MOSFETs MN1 and MP1 will mix these quadratic terms with the linear terms in the voltage signal Vin being applied to the gates of transistors MN1 and MP1 to generate a significant amount of third order distortion which otherwise would not exist without the resistive degeneration.
Similarly, the negative feedback in a resistively degenerated P-channel transistor circuit as in FIG. 3 tries to suppress the total distortion of resistively degenerated PMOS transconductor circuits which are otherwise dominated by second-order distortion. The graphs included in FIG. 3 illustrate the generation of such third order distortion.
Note that a more detailed analysis of resistive degeneration in MOS transistors and CMOS transconductors is set forth in the cited publication “RF Transconductor Linearization Technique Robust to Process, Voltage and Temperature Variations” by present inventors Harish Kundur Subramaniyan, Eric Klumperink, Venkatesh Srinivasan, Ali Kiaei, and Brain Nauta, presented at the IEEE Asian Solid-State Circuits Conference in Kaohsiung, Taiwan Nov. 10-12, 2014.
To summarize, a CMOS inverter is an efficient transconductor, because the same bias current flows through both the NMOS and PMOS transistors, resulting in addition of their transconductances gmn and gmp and consequently resulting in higher gm/ID ratio or higher power efficiency. A purely differential circuit does not suffer from even order distortion, so it is desirable to reduce the odd-order distortion coefficients more than the even order distortion coefficients.
Thus, there is an unmet need for a CMOS-based transconductor circuit having better linearity than prior CMOS transconductor circuits utilizing cancellation of non-linear current components in the P-channel and N channel transistors of a CMOS inverter.
There also is an unmet need for a CMOS-based transconductor circuit which has better linearity than prior CMOS transconductor circuits utilizing cancellation of non-linear current components in the P-channel and N channel transistors of a CMOS inverter and which also is more robust with respect to PVT (Process, supply Voltage, and Temperature) variations.
There also is an unmet need for a CMOS-based transconductor circuit which achieves better linearity than prior CMOS transconductor circuits utilizing cancellation of non-linear current components in the P-channel and N channel transistors of a CMOS inverter by avoiding linearity degradation that occurs in prior CMOS transconductor circuits utilizing resistor degeneration.
There also is an unmet need for a CMOS-based transconductor circuit which achieves better linearity than prior art CMOS transconductor circuits without substantially degrading transconductor noise performance.
There also is an unmet need for a CMOS-based transconductor circuit which achieves better linearity than prior CMOS transconductor circuits utilizing cancellation of non-linear current components in the P-channel and N channel transistors of a CMOS inverter by avoiding linearity degradation that occurs in prior CMOS transconductor circuits utilizing resistor degeneration and which also does not introduce substantial additional noise compared to prior CMOS transconductor circuits utilizing resistor degeneration.